A single event upset (SEU) occurs in an electronic circuit device, such as a digital circuit, when the device is exposed to energetic ions and protons. This is a particular concern for circuit devices that are to be deployed for operation in space, such as Earth orbit.
In harsh environments, such as space, where digital circuits are exposed to radiation, many processors may be prone to single event functional interrupts (SEFIs). A SEFI impairs the normal operation of the host device and requires a reboot or power cycle. Further evaluations have shown that that a significant portion of those SEFIs take the form of TLB miss exceptions.
In processor devices, a translation lookaside buffer (TLB) is a hardware component that is provided to improve the speed of virtual to physical address translations. A TLB comprises an array of entries that maps a virtual address region to a corresponding physical address region. If a single bit erroneously changes within the TLB array, the system will likely fail when the corrupt entry is accessed and an improper address translation is triggered.
A TLB miss exception is triggered when a processor attempts a translation of a virtual address to a physical address using a translation lookaside buffer that does not contain an entry for the virtual address in question. A TLB miss exception can be caused by either looking up an invalid virtual address in a valid TLB array or by looking up a valid virtual address in an invalid TLB array.